This invention relates to semiconductor memory devices and individual memory cells comprising components thereof and, more particularly, to a memory cell for a MOS random access memory (RAM) device which utilizes a buried sense line and a V-groove anisotropical etch to access it, thereby increasing the packing density of the RAM cells for the device.
The use of MOS random access memory devices is already extensive and continues to increase. Since the introduction of 1kbit MOS dynamic RAMs in 1970, development has progressed rapidly to the point that semiconductor memories are now preferred over core. Because most of the cost associated with the production of these memory devices derives from bonding, packaging, testing and handling, rather than from the production of the circuitry on the chip, recent development in this area has focused on methods for increasing the density of the memory cells contained on a given chip of silicon rather than on methods for increasing the efficient operation of the chip itself or on the simplification of the associated sensing and amplifier circuitry. Consequently 4 kbit RAMs are now in wide production, 16 kbit RAMs are becoming more common, and several semiconductor companies are expected to begin volume production of 64 and 256 kbit RAMs in the near future.
Several types of MOS RAMs are available; these devices fall into three broad categories. First, and most common, are the semiconductor memory cells of the one-transistor type such as that described in U.S. Pat. No. 3,909,631, issued Sept. 30, 1975 to N. Kitagawa, and pending applications Ser. No. 648,594, filed Jan. 12, 1976 by C-K. Kuo and Ser. No. 691,735 filed June 1, 1976 by White, McAdams and Redwine, now U.S. Pat. No. 4,081,701 issued Mar. 28, 1978. The one-transistor cell is also described in detail in Electronics, Sept. 13, 1973 at pp. 116-121 and Electronics, May 13, 1976 at pp. 81-86. The second type of semiconductor memory cell is the MOS RAM cell concept which utilizes double level polysilicon gates, such as that described in pending application Ser. No. 803,495, filed June 6, 1977 by C-K. Kuo. Finally, a third type of MOS RAM is the so-called charge coupled RAM, such as that disclosed in pending application Ser. No. 554,889, filed Mar. 3, 1975 by Al F. Tasch, Jr. et al abandoned in favor of continuation application Ser. No. 739,758 filed Nov. 8, 1976, now U.S. Pat. No. 4,060,738 issued Nov. 29, 1977 and which is described in the IEEE Journal of Solid State Circuits, Vol. SC-11, No. 1 (February 1976), pp. 58-63, and in IEEE Journal of Solid State Circuits, Vol. SC-11, No. 5 (October 1976), pp. 575-585.
Although each of these types of prior art MOS RAMs differ in operational characteristics and each has its own advantages and disadvantages, certain structural features are common to all conventional MOS RAMs. A one-transistor MOS RAM cell and a double-level polysilicon MOS RAM cell are shown in FIGS. 10A and B respectively at p. 583 of the IEEE Journal of Solid State Circuits, Vol. SC-11, No. 5 (October 1976). A charge coupled MOS RAM is shown in FIG. 1A of the same article at p. 575. As indicated in these figures, the cell is usually fabricated on a block of P type silicon substrate material and utilizes a bit (or sense) line of diffused N.sup.+ material near the surface of the device and separated from the transfer gate by a layer of silicon dioxide. The cells are all fabricated so that there is a storage region, formed by a small geometry capacitor, and a transfer region, formed by a small geometry transistor, adjacent to each other near the surface of the device, the transfer region being laterally disposed between the N.sup.+ diffused sense line and the storage region. The transistor thus connects the sense line and the storage region and provides selective isolation between the two. A binary "1" may be written into the RAM cell by pulsing the transfer gate, thereby turning on the transistor, and allowing charge to collect on the capacitor. A binary "0" may be similarly written into the cell by not allowing charge to flow into the capacitor. The transistor may then be turned off to store the information. The charge or absence thereof may be detected by the sense line in conjunction with selective clocking of the transfer gate. The physical structure of these prior art RAM cells has several inherent disadvantages.
First, because the N.sup.+ bit line diffusion in conventional RAMs is performed as a later step in the fabrication process, the doping level of this layer is limited because the heating required to introduce a high level of impurities at this step could interfere with impurity levels which have already been introduced at the surface of the device, as in the case of the double implant at the surface of a charge coupled MOS RAM cell. However, it is desirable to make the impurity level in the sense line layer as high as possible in order to reduce the sheet line resistance of the sense line, since a decrease in the sheet line resistance results in a reduction of the RC time constant which is associated with the sense line and which is a limitation on the data rate available therethrough.
Second, because the sense line in conventional RAMs is near the surface of the device and is separated from the transfer gate by only a thin layer of silicon dioxide, the clocking of the transfer gate introduces small voltages along the sense line because of the capacitive coupling between the gate and the sense line which must be filtered by the external amplifier circuitry in order to avoid errors in the operation of the device.
Because the storage region must be logically connected with the sense line through the transfer region, these regions are conventionally fabricated next to each other at the surface of the chip, the result being an inherent loss in density, which is limited by the sum of the physical widths of the three regions.
In addition, fabrication complexity is introduced by the use of the charge coupled RAM concept, which utilizes a double implant of P and N type impurities at the surface of the device, as shown in FIG. 1, page 575 of the article appearing in the IEEE Journal of Solid State Circuits, Vol. SC-11, No. 5 (October 1976). As described in the discussion of that figure, the storage region contains a shallow N type ion implant and a relatively deeper P type ion implant while the transfer region is free of implants. It is critical that the edge of the P type implant at the boundary of the two regions either coincides with or lies inside of the N type implant in order to avoid a potential barrier in the transfer region which would destroy the read/write operation of the cell. Failure to properly align these regions results in a defective device, and the alignment tolerance is therefore a critical measure of reliability in the fabrication process of a conventional charge coupled RAM cell.